1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2010-227908, filed Oct. 7, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recent years, the gate length of a MOS (Metal Oxide Semiconductor) transistor has been reduced in accordance with rapid miniaturization of elements such as a DRAM (Dynamic Random Access Memory). Also, the distance between the adjacent MOS transistors has been reduced by integrating a lot of MOS transistors in a memory cell region. The short gate length may cause a deterioration of transistor properties by a short-channel effect of the MOS transistor.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2007-180150 discloses a buried-gate MOS transistor which is one measure for suppressing the short-channel effect of the MOS transistor. The buried-gate MOS transistor sufficiently secures an effective channel length (gate length) physically. Therefore, the buried-gate MOS transistor can realize a miniaturized DRAM. Since the buried-gate MOS transistor is suitable for high-integration, it is considered that the buried-gate MOS transistor is used as a cell transistor of the DRAM.